HCL:Dragino LG02

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The Dragino LG02 and OLG02 are MIPS based dual-channel LoRa gateways, shipping with OpenWrt.

Technical details

  • Dragino HE SoM
    • Atheros AR9331 SoC
      • 1x MIPS CPU @ 400 MHz
  • Dragino LoRa G-Dual daughterboard
    • 2x HopeRF RFM9x LoRa modules (SPI)
      • Semtech SX127x LoRa transceiver
  • 2x Ethernet
  • 1x USB 2.0
  • XBee socket

Manual installation

Beneath the daughterboard there's a connector with labeled RXD, TXD, GND pins that expose the serial console.

Note: A mips port of openSUSE is not bootstrapped yet.


The device ships a downstream U-Boot 1.1.4.

As of v2018.11-rc3, mainline U-Boot has some support for ar933x but no configs for Dragino boards.


The mainline kernel does have support for ar9331, but no Device Tree for LG02 or HE. (Being prepared on dragino-next branch.)

$ make ARCH=mips CROSS_COMPILE=mips-suse-linux- ath79_defconfig


$ make ARCH=mips CROSS_COMPILE=mips-suse-linux- vmlinux.bin dtbs
$ cat arch/mips/boot/vmlinux.bin arch/mips/boot/dts/qca/ar9331_dragino_lg02.dtb > vmlinux_dtb.bin
$ mkimage -A mips -O linux -T kernel -C none \
          -a 0xffffffff80060000 -e $(arch/mips/tools/elf-entry vmlinux) \
          -d vmlinux_dtb.bin uImage

To boot from TFTP:

dr_boot> tftpboot $loadaddr uImage
dr_boot> bootm $loadaddr

Unfortunately this does not yet reliably boot as of v4.20-rc1.

See also