HCL:DE0-Nano-SoC
The DE0-Nano-SoC is a compact (68.59x96mm) board. It is manufactured by Terasic.
Technical Data
- Intel (Altera) Cyclone® V SE 5CSEMA4U23C6N SoC
- 2x ARM Cortex-A9 CPU @ 925 MHz
- 1 GB DDR3 SDRAM
- 1 Gigabit Ethernet
- MicroSD card connector
- onboard USB-Blaster II
- Arduino expansion header (Uno R3 compatibility)
- A/D converter
- USB OTG Port
- Accelerometer
- UART to USB serial console
- Two 40-pin expansion header
Writing a disk image to the SD card
- Download the image you want (Leap is stable, Tumbleweed is rolling) from here:
TumbleweedJeOS image If the direct links above do not work for you, please check the general download directory for the images.
Leap-15.3JeOS image If the direct links above do not work for you, please check the general download directory for the images.
- As root extract the image onto your SD card (replace sdX with the device name of your SD card).
WARNING: all previous data on the SD card will be lost. Check first if the device you have selected is really your SD card!xzcat [image].raw.xz | dd bs=4M of=/dev/sdX iflag=fullblock oflag=direct; sync
- Insert the SD card with the openSUSE image into your board.
- Connect the board to your PC via serial port (optional, but helpful for debugging; USB-TTL serial cable needed).
- Connect the board to your monitor (via DVI/HDMI, optional).
- Power on the board.
- Walk through the first boot steps.
- Ethernet is configured to request an IP via DHCP, check your DHCP server for the board IP if used.
- Have a lot of fun...
Watchdog
The upstream u-boot enables the first of the two watchdogs that the FPGA supports. The DE0-nano-SoC image includes a boot.scr file on the first (EFI) partition, which disables the first watchdog. This avoids a watchdog trigger during the MMC re-partition phase during the first start. To enable the watchdog, the boot.scr needs to be modified and the dw_wdt.ko module needs to be loaded during Linux startup.
FPGA Bitfile
There are three basic ways to load bit files to the FPGA:
- Flash the bit file to the on-board EPCS128. For this the Quartus programmer software and a USB cable is needed. The FPGA is configured automatically before any software is started.
- Load and configure the FPGA with bit file by u-boot. The DE0-nano-SoC image includes a boot.scr file on the first (EFI) partition, which loads per default from the same partition with the file name fpga.rbf or atlas_soc_ghrd.rbf.
- Load and configure the FPGA with bit file during driver load by Linux firmware API. This requires a driver that triggers the firmware load via the Linux FPGA loader infrastructure.
boot.scr
The DE0-nano-SoC image includes a boot.scr file on the first (EFI) partition. This is loaded and executed by u-boot before the EFI boot image is loaded. To modify this edit on the first partition the boot.script file (on the system this partition is mounted to /boot/efi) and then convert it by the following command:
mkimage -A arm -O linux -a 0 -e 0 -T script -C none -n 'Boot-Script' -d boot.script boot.scr